The present invention relates generally to the field of integrated circuit technology. The present invention provides an improved lock detection circuit that indicates when an output phase is locked to an input phase in a phase locked loop circuit.
Phase locked loop circuits are well known. FIG. 1 illustrates a block diagram of a prior art frequency synthesizer charge pump phase locked loop (PLL) circuit 100. Input signal FIN is provided to input divider 110 and the output of input provider 110 is provided to a first input of phase frequency detector 120. Phase frequency detector 120 provides an xe2x80x9cupxe2x80x9d signal (designated xe2x80x9cUPxe2x80x9d) and a xe2x80x9cdownxe2x80x9d signal (designated xe2x80x9cDNxe2x80x9d) to charge pump 130. As is well known in the art, the UP signal closes a switch to cause current source 140 to provide current Iup to the output line of charge pump 130. The DN signal closes a switch to cause current source 150 to draw current IDN from the output line of charge pump 130.
The output line of charge pump 130 is coupled to loop filter 160 and to voltage controlled oscillator 170. The currents from charge pump 130 adjust the phase of the voltage controlled oscillator 170. The output signal For from voltage controlled oscillator 170 is provided to feedback divider 180. The output of feedback divider 180 is provided to a second input of phase frequency detector 120.
A charge pump PLL is a negative feedback system that insures that the phase difference as well as the frequency difference at the input of phase frequency detector 120 is near zero under steady state conditions. A PLL in such a state is said to be in a xe2x80x9clockxe2x80x9d condition or xe2x80x9clocked.xe2x80x9d The input and output frequencies are related by a fixed ratio which can be selected by choosing the values of the input divider 110 and the feedback frequency divider 180.
A charge pump PLL is typically a second order system. Therefore, any change from the steady state condition will result in a transient response that is typically characterized by the damping factor and the natural frequency of the system. The damping factor and the natural frequency of the system are dependent upon physical quantities such as the charge pump current, the effective gain of the voltage controlled oscillator 170, parameters of the loop filter 160, and properties of the phase frequency detector 120. The settling behavior of the transient response may also be governed by the comparison frequency at the input of the phase frequency detector 120.
Because some of these parameters are not constant, the time required for the PLL to acquire lock will vary. The output frequency of the PLL before it acquires lock is not stable and should therefore not be used. Because the charge pump PLL is second order system, there will be some overshoots and some undershoots in the transient response signal.
A lock detection circuit can be constructed that is capable of indicating the locked or unlocked state of the PLL circuit. Various methods exist for implementing a lock detection circuit. The implementation may be either analog or digital. Most prior art implementations rely on monitoring the activity at the output of the phase frequency detector 120 and some sort of analog filtering. For a lock detection signal to be of practical use, the signal should remain stable, should be insensitive to various mismatches in the loop, and should be tolerant to noise, and should have minimum latency.
The output of a Type IV phase frequency detector in a charge pump PLL comprises pulses at the UP output pin and at the DN output pin such that the difference in the pulse widths of the UP signal and the DN signal is equal to the input phase difference. The UP and DN signals are provided to charge pump 130. In response, charge pump 130 dumps an equivalent charge to adjust the phase of the voltage controlled oscillator 170. In a locked state, the output of phase frequency detector 120 comprises narrow pulses of equal duration on the UP output pin and on the DN output pin. The use of narrow pulses even in the locked state prevents the formation of a dead zone for small phase differences at the input of phase frequency detector 120.
There are deviations from ideal behavior in a practical system. For example, the xe2x80x9cupxe2x80x9d current Iup and the xe2x80x9cdownxe2x80x9d current IDN in charge pump 130 are not exactly equal due to the finite output impedance of current source 140 and current source 150. There can also be delay mismatches between the UP signal and the DN signal at the output of phase frequency detector 120. Leakage in loop filter 160 may also affect the operation of the charge pump PLL system.
Because the charge pump PLL system is a negative feedback system, the PLL corrects for all the non-ideal conditions by having a small phase offset at the input of the phase frequency detector 120 of an appropriate magnitude and polarity to negate these effects. This phase difference at the input of the phase frequency detector 120 is called the xe2x80x9cstatic phase error.xe2x80x9d
Random noise from individual components within the PLL circuit or from the power supply (not shown) could lead to an occasional pulse (or pulses) at the output of the phase frequency detector 120. An occurrence of such a pulse (or pulses) does not technically amount to an unlocked condition. Unless proper care is taken in designing a lock detection circuit, such a pulse (or pulses) may appear as an erroneous signal or glitch in the xe2x80x9clockxe2x80x9d signal.
It would be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of detecting when an output phase is locked and is not locked to an input phase in the phase locked loop circuit.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of generating a lock signal that is stable.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is capable of generating a lock signal that is insensitive to mismatches within individual circuit elements within the phase locked loop circuit.
It would also be desirable to have a lock detection circuit in a phase locked loop circuit that is tolerant of noise and that has minimum latency.
The present invention is directed to an apparatus and method for providing a lock detection circuit in a phase locked loop circuit that is capable of detecting when an output phase is locked to an input phase in the phase locked loop circuit, and when an output phase is not locked to an input phase in the phase locked loop circuit.
An advantageous embodiment of the present invention comprises an exclusive OR gate, a deglitch unit, a gate circuit, a count lock circuit, a count unlock circuit, and a D flip flop circuit. The exclusive OR gate receives an UP signal and a DN signal from a phase frequency detector. The exclusive OR gate filters out those portions of an UP signal and those portions of a DN signal that occur at the same time. The output of the exclusive OR gate represents either (1) a portion of an UP signal that occurs when a DN signal is not present, or (2) a portion of a DN signal that occurs when an UP signal is not present.
The deglitch unit outputs a clear xe2x80x9cclrxe2x80x9d signal pulse only when the UP and DN signals are mismatched in time by more than a predetermined period of time. The delay time is equal to (or slightly greater than) the estimated static phase error of the PLL when it is locked.
The detection of a locked or an unlocked state within the PLL is made by processing xe2x80x9cdclrxe2x80x9d l signal pulses. The xe2x80x9cclrxe2x80x9d signal pulses are coupled to a first input of gate circuit and also are coupled to a count unlock circuit. When the PLL is not in a locked condition, the gate circuit passes each xe2x80x9cclrxe2x80x9d signal pulse to a count lock circuit to reset a counter within the count lock circuit that is counting clock cycles. In the absence of a xe2x80x9cclrxe2x80x9d signal pulse for a fixed number of clock cycles, the count lock circuit determines that the PLL is locked. The count lock circuit then outputs a ready xe2x80x9crdyxe2x80x9d signal to a D flip flop that sets a xe2x80x9clockxe2x80x9d signal. The xe2x80x9clockxe2x80x9d signal is coupled to a second input of the gate circuit.
After the PLL is in a locked condition, the lock detection circuit of the present invention looks for an unlocked condition. The gate circuit blocks any xe2x80x9cclrxe2x80x9d signal pulses from resetting the counter in the count lock circuit. The count lock circuit now counts clock cycles and outputs a reset xe2x80x9crstxe2x80x9d signal pulse to the count unlock circuit after the count lock circuit counts a predetermined number of clock cycles.
The count unlock circuit counts the number of xe2x80x9cclrxe2x80x9d signal pulses received from the deglitch unit between two xe2x80x9crstxe2x80x9d signal pulses received from the count lock circuit. When the number of xe2x80x9cclrxe2x80x9d signal pulses received exceeds a predetermined number between two xe2x80x9crstxe2x80x9d signal pulses, the count unlock circuit then outputs an xe2x80x9cunlockxe2x80x9d signal to clear the D flip flop. This causes the xe2x80x9clockxe2x80x9d signal to go low indicating that the PLL is in an unlocked condition.
The lock detection circuit of the present invention operates by cycling back and forth between searching for the occurrence of an unlocked condition when the PLL is locked, and searching for the occurrence of a locked condition when the PLL is unlocked.
It is an object of the present invention to provide an apparatus and method for providing a lock detection circuit for a phase locked loop circuit that is capable of generating a lock signal that is stable.
It is another object of the present invention to provide an apparatus and method for providing a lock detection circuit for a phase locked loop circuit that is capable of generating a lock signal that is insensitive to mismatches within individual circuit elements within the phase locked loop circuit.
It is also an object of the present invention to provide an apparatus and method for providing a lock detection circuit for a phase locked loop circuit that is tolerant of noise and that has minimum latency.
It is another object of the present invention to provide an apparatus and method for providing a lock detection circuit for a phase locked loop circuit that is capable of ignoring one or more pairs of occasionally mismatched UP signals and DN signals from a phase frequency detector when the phase locked loop circuit is in a locked condition.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the Detailed Description of the Invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject matter of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the Detailed Description of the Invention, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: The terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprisexe2x80x9d and derivatives thereof, mean inclusion without limitation, the term xe2x80x9corxe2x80x9d is inclusive, meaning xe2x80x9cand/orxe2x80x9d; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, to bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontroller,xe2x80x9d xe2x80x9cprocessor,xe2x80x9d or xe2x80x9capparatusxe2x80x9d means any device, system or part thereof that controls at least one operation. Such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document. Those of ordinary skill should understand that in many instances (if not in most instances), such definitions apply to prior, as well as future uses of such defined words and phrases.